The invention relates to a semiconductor device comprising a semiconductor body having a region of a first conductivity type adjoining a surface of the semiconductor body, which semiconductor body is provided at the surface with a non-volatile memory cell comprising a source and a drain of an opposite, second conductivity type provided in the semiconductor body, between which source and drain the surface of the semiconductor body is provided with a floating gate and a select gate, the floating gate and the select gate both having a substantially flat surface portion extending substantially parallel to the surface of the semiconductor body and having side-wall portions extending substantially transversely to the surface of the semiconductor body, above which floating gate a control gate is situated, which control gate overlaps the select gate.
Such a non-volatile memory cell, which is often referred to as an EEPROM (Electrically Erasable Programmable Read-Only Memory) cell, comprises at least one select transistor and a field-effect transistor with floating gate, also referred to as floating gate transistor.
A semiconductor device of the kind mentioned in the opening paragraph is known from EP-A-763 856. In the known semiconductor device the control gate stretches out over the select gate to substantially beyond the side-wall portion of the select gate facing away from the floating gate.
A disadvantage of the known semiconductor device is that the size of the memory cell is large owing to the fact that the control gate extends out to substantially beyond the sidewall portion of the select gate facing away from the floating gate. As a consequence, the density of memory cells in a non-volatile memory of a given size is small. In addition, parasitic capacitances are induced between the control gate and the select gate as a result of the closeness between the control gate and the select gate during operation of the memory cell, which parasitic capacitances adversely increase the RC time of the select gate. Moreover, it is not possible to subject the select gate of the memory cell to a self-aligned silicide process, also referred to as salicide process, to reduce its sheet and contact resistance. Hence, the resistance of the select gate is large, which also adversely influences the RC time of the select gate.